The considerable expansion in the market of portable applications utilizing non-volatile memory devices, above all Flash memory devices, has notably increased the request of devices with high integration and low power consumption. Such memory devices are not naturally formed to operate with a low power consumption because high voltages must be utilized to move charges in the insulated gate during the erasing and programming operations, the voltages are generated for the most part internally by charge pumps. Thus, a main problem for such non-volatile memory devices, is in the power consumption thereof.
In a CMOS device it is generally known that the power consumption derives both from a static power consumption and a dynamic power consumption. The static power consumption depends essentially on the bias and leakage currents, while the dynamic power consumption is due mainly to the current transistors during the commutations and to charging and discharging the capacitive nodes. However it is generally known that in the digital devices the static consumption is negligible with respect to the dynamic consumption.
In a digital circuit utilizing capacitive nodes with potential transactions between voltage levels which code logic signals, generally the ground voltage for the logic level 0 and the supply voltage for the logic level 1, the dynamic power consumption can be expressed by the following relation:
Pdiss proportional to f.sub.* Vdd.sup.2* AiCi
wherein Ci represents the charge capacity of the node i-eth summed up the N circuit nodes, f is the work frequency of the circuit, Vdd is the supply voltage, Ai is the activity factor (number of gates switching with respect to the total gate number) at the node i.
A non volatile memory device of the EPROM, EEPROM or Flash type is usually formed by a matrix structure where the memory cells are organized by rows and columns and comprise MOS transistors having each one a floating gate. The reading, writing and erasing operations of the memory cells are effectuated by applying suitable voltages to the row and column, which are selected by a row and a column decoder, and to the source line.
In the aforementioned operations the nodes of the memory cell which are connected to the suitable voltage suffer transactions among the different potential levels and this allows to charge and to discharge the parasitic capacities connected to the row, column and source line of the cell. In fact, if we consider, for example, a writing operation in the memory cell belonging to a first row and column, the first column must be connected to a prefixed voltage (for example it is comprised between 4V and 6V if the supply voltage is 5V) and the first row to a considerably higher voltage than the supply voltage (for example it is comprised between 10V and 12V and provided by a charge pump). A successive writing in another memory cell belonging to a second row and column causes the discharge of the first row and column and the connection of the second row and column to prefixed voltages.
However the memory cell reading, writing and erasing operations cause a considerably power consumption, above all in the writing and erasing operations wherein the voltages used are high, because the power used in the rows or columns or source lines of the memory cells already read or written or erased cannot be reutilized.